Sciweavers

VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
14 years 12 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
14 years 12 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
VLSID
2002
IEEE
129views VLSI» more  VLSID 2002»
14 years 12 months ago
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylves...
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
14 years 12 months ago
A Framework for Design Space Exploration of Parameterized VLSI Systems
The paper presents two new approaches to multiobjective design space exploration for parametric VLSI systems. Both considerably reduce the number of simulations needed to determin...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
14 years 12 months ago
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
Sanjukta Bhanja, N. Ranganathan
VLSID
2003
IEEE
109views VLSI» more  VLSID 2003»
14 years 12 months ago
Living at the Edge
Ted Vucurevich
VLSID
2003
IEEE
108views VLSI» more  VLSID 2003»
14 years 12 months ago
A Low Power-Delay Product Page-Based Address Bus Coding Method
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
VLSID
2003
IEEE
148views VLSI» more  VLSID 2003»
14 years 12 months ago
Extending Platform-Based Design to Network on Chip Systems
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell,...
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 12 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...