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VLSID
2002
IEEE
132views VLSI» more  VLSID 2002»
14 years 12 months ago
VLSI Architecture for a Flexible Motion Estimation with Parameters
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsu...
VLSID
2002
IEEE
102views VLSI» more  VLSID 2002»
14 years 12 months ago
Losses in Multilevel Crossover in VLSI Interconnects
The radiation and surface wave losses may give rise to electromagnetic interference (EMI) problems in high speed VLSI interconnects. Over and above there will be dielectric and co...
P. K. Datta, S. Sanyal, D. Bhattacharya
VLSID
2002
IEEE
130views VLSI» more  VLSID 2002»
14 years 12 months ago
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...
Anupam Datta, Sidharth Choudhury, Anupam Basu
VLSID
2002
IEEE
90views VLSI» more  VLSID 2002»
14 years 12 months ago
Software-Only Bus Encoding Techniques for an Embedded System
Microprocessors with built-in Liquid Crystal Device (LCD) controllers and equipped with Flash ROM are common in mobile computing applications. In the first part of the paper, a so...
Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 12 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 12 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
VLSID
2002
IEEE
109views VLSI» more  VLSID 2002»
14 years 12 months ago
Probabilistic Analysis of Rectilinear Steiner Trees
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
Chunhong Chen
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
14 years 12 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
14 years 12 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
VLSID
2002
IEEE
82views VLSI» more  VLSID 2002»
14 years 12 months ago
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Raj...