VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
VLSID
2002
IEEE
14 years 12 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...