- This paper presents a methodology for concurrently optimizing an IC fabrication process and a standard cell library in order to maximize overall yield. The approach uses the Conc...
Arun N. Lokanathan, Jay B. Brockman, John E. Renau...
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...
Abstract: Exploration at the earliest stages of the design process is an integral component of effective low-power design. Nevertheless, superficial high-level analyses with insuff...
In this paper, we describe a system design methodology for the concurrent development of hybrid software/hardware systems for telecom network applications. This methodology is bas...
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
We offer a technique to partition a centralized control-flow graph to obtain distributed control in the context of asynchronous highlevel synthesis. The technique targets Huffman-...
Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Ja...
Abstract A divide-and-conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could...
Boundary element methods (BEM) are often used for complex 3-D capacitance extraction because of their efficiency, ease of data preparation, and automatic handling of open regions. ...
Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T....