Sciweavers

DAC
1996
ACM
14 years 3 months ago
Error Correction Based on Verification Techniques
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
DAC
1996
ACM
14 years 3 months ago
A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines
Abstract-- This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is like...
Hiroyuki Higuchi, Yusuke Matsunaga
DAC
1996
ACM
14 years 3 months ago
Improved Tool and Data Selection in Task Management
Task management involves task creation and execution. These are facilitated using a task schema as exemplified in the Hercules Task Manager. Experience with Hercules has shown the...
John W. Hagerman, Stephen W. Director
DAC
1996
ACM
14 years 3 months ago
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
Laurence Goodby, Alex Orailoglu
DAC
1996
ACM
14 years 3 months ago
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction
In this paper, we describe how we have improved the efficiency of a finite-element method for interconnect resistance extraction by introducingarticulation nodes in the finiteelem...
Arjan J. van Genderen, N. P. van der Meijs
DAC
1996
ACM
14 years 3 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou
DAC
1996
ACM
14 years 3 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
DAC
1996
ACM
14 years 3 months ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
DAC
1996
ACM
14 years 3 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen