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    VLSISP
    2010
    205views more  VLSISP 2010»
    Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA
    14 years 6 days ago
    Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA
    Download  rtsimage.di.uoa.gr
    — This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, s...
    Dimitris G. Bariamis, Dimitris Maroulis, Dimitrios...
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    LATINCRYPT
    2010
    172views Cryptology» more  LATINCRYPT 2010»
    Accelerating Lattice Reduction with FPGAs
    14 years 8 days ago
    Accelerating Lattice Reduction with FPGAs
    Download  perso.ens-lyon.fr
    We describe an FPGA accelerator for the Kannan–Fincke– Pohst enumeration algorithm (KFP) solving the Shortest Lattice Vector Problem (SVP). This is the first FPGA implementati...
    Jérémie Detrey, Guillaume Hanrot, Xa...
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    VLSISP
    2002
    199views more  VLSISP 2002»
    Evaluation of CORDIC Algorithms for FPGA Design
    14 years 1 months ago
    Evaluation of CORDIC Algorithms for FPGA Design
    Download  bwrc.eecs.berkeley.edu
    Abstract. This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the...
    Javier Valls, Martin Kuhlmann, Keshab K. Parhi
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    TCAD
    2002
    134views more  TCAD 2002»
    Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
    14 years 1 months ago
    Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
    Download  testlab.ics.uci.edu
    As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...
    Ian G. Harris, Russell Tessier
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    TVLSI
    1998
    123views more  TVLSI 1998»
    On-line fault detection for bus-based field programmable gate arrays
    14 years 1 months ago
    On-line fault detection for bus-based field programmable gate arrays
    Download  www.cs.ucla.edu
    Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
    N. R. Shnidman, William H. Mangione-Smith, Miodrag...
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    TC
    1998
    108views Information Technology» more  TC 1998»
    Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
    14 years 1 months ago
    Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
    Download  www.ece.uic.edu
    —The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
    Fran Hanchek, Shantanu Dutt
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    DT
    1998
    85views more  DT 1998»
    How Much Logic Should Go in an FPGA Logic Block?
    14 years 1 months ago
    How Much Logic Should Go in an FPGA Logic Block?
    Download  www.eecg.toronto.edu
    The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related ...
    Vaughn Betz, Jonathan Rose
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    JUCS
    2000
    135views more  JUCS 2000»
    The Price of Routing in FPGAs
    14 years 1 months ago
    The Price of Routing in FPGAs
    Download  perso.ens-lyon.fr
    : Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to r...
    Florent de Dinechin
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    MAM
    2007
    157views more  MAM 2007»
    Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
    14 years 1 months ago
    Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
    Download  www.cse.secs.oakland.edu
    This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
    Darrin M. Hanna, Michael DuChene
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    TVLSI
    2008
    111views more  TVLSI 2008»
    GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
    14 years 1 months ago
    GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
    Download  www.ece.ubc.ca
    This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
    Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
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