—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
Robert Schwencker, Josef Eckmueller, Helmut E. Gra...
We study alternatives to FM-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instan...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
One subtask in constraint-driven placement is enforcing a set of orientation constraints on the devices being placed. Such constraints are created in order to, for example, implem...