- We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory p...
Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek...
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. W...
We extend an existing probabilistic congestion model to consider shielding for crosstalk reduction. We then develop a multilevel router to study the impact of various congestion m...
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Abstract— ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a repre...
- It is important to model the substrate coupling for mixed-signal circuit designs today. This paper presents the direct boundary element method (BEM) for substrate resistance calc...
Abstract — TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TE...
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...
Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanya...