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ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Fast synthesis of exact minimal reversible circuits using group theory
- We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory p...
Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek...
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
14 years 1 months ago
On multiple-voltage high-level synthesis using algorithmic transformations
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
Hsueh-Chih Yang, Lan-Rong Dung
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
14 years 1 months ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
ASPDAC
2005
ACM
114views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Redundant-via enhanced maze routing for yield improvement
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. W...
ASPDAC
2005
ACM
94views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Probabilistic congestion model considering shielding for crosstalk reduction
We extend an existing probabilistic congestion model to consider shielding for crosstalk reduction. We then develop a multilevel router to study the impact of various congestion m...
Jinjun Xiong, Lei He
ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
ASPDAC
2005
ACM
105views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Interconnect estimation without packing via ACG floorplans
Abstract— ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a repre...
Jia Wang, Hai Zhou
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Substrate resistance extraction with direct boundary element method
- It is important to model the substrate coupling for mixed-signal circuit designs today. This paper presents the direct boundary element method (BEM) for substrate resistance calc...
Xiren Wang, Wenjian Yu, Zeyi Wang
ASPDAC
2005
ACM
72views Hardware» more  ASPDAC 2005»
14 years 1 months ago
TERPS: the embedded reliable processing system
Abstract — TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TE...
Hongxia Wang, Samuel Rodríguez, Cagdas Diri...
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
14 years 1 months ago
An LP-based methodology for improved timing-driven placement
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...
Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanya...