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    ASPDAC
    2010
    ACM
    133views Hardware» more  ASPDAC 2010»
    Checker-pattern and shared two pixels LOFIC CMOS image sensors
    13 years 9 months ago
    Checker-pattern and shared two pixels LOFIC CMOS image sensors
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    Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigeto...
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    ASPDAC
    2010
    ACM
    117views Hardware» more  ASPDAC 2010»
    Variation tolerant logic mapping for crossbar array nano architectures
    13 years 9 months ago
    Variation tolerant logic mapping for crossbar array nano architectures
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    Cihan Tunc, Mehdi Baradaran Tahoori
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    ASPDAC
    2010
    ACM
    161views Hardware» more  ASPDAC 2010»
    A dual-MST approach for clock network synthesis
    13 years 9 months ago
    A dual-MST approach for clock network synthesis
    Download  www.cse.cuhk.edu.hk
    Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
    Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
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    ASPDAC
    2010
    ACM
    137views Hardware» more  ASPDAC 2010»
    Managing verification error traces with bounded model debugging
    13 years 9 months ago
    Managing verification error traces with bounded model debugging
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    Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior...
    Sean Safarpour, Andreas G. Veneris, Farid N. Najm
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    ASPDAC
    2010
    ACM
    110views Hardware» more  ASPDAC 2010»
    An alternative polychronous model and synthesis methodology for model-driven embedded software
    13 years 9 months ago
    An alternative polychronous model and synthesis methodology for model-driven embedded software
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    Bijoy A. Jose, Sandeep K. Shukla
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    ASPDAC
    2010
    ACM
    121views Hardware» more  ASPDAC 2010»
    Current source modeling in the presence of body bias
    13 years 9 months ago
    Current source modeling in the presence of body bias
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    Saket Gupta, Sachin S. Sapatnekar
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    ASPDAC
    2010
    ACM
    166views Hardware» more  ASPDAC 2010»
    -Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase
    13 years 9 months ago
    -Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase
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    Koichiro Yamashita
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    ASPDAC
    2010
    ACM
    105views Hardware» more  ASPDAC 2010»
    Physical design techniques for optimizing RTA-induced variations
    13 years 9 months ago
    Physical design techniques for optimizing RTA-induced variations
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    Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapat...
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    ASPDAC
    2010
    ACM
    105views Hardware» more  ASPDAC 2010»
    Simultaneous slack budgeting and retiming for synchronous circuits optimization
    13 years 9 months ago
    Simultaneous slack budgeting and retiming for synchronous circuits optimization
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    Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang
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    ASPDAC
    2010
    ACM
    183views Hardware» more  ASPDAC 2010»
    Multi-operand adder synthesis on FPGAs using generalized parallel counters
    13 years 9 months ago
    Multi-operand adder synthesis on FPGAs using generalized parallel counters
    Download  qir.kyushu-u.ac.jp
    Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...
    Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
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