Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, Jo...
Abstract-- We develop a rational function macromodeling algorithm named VISA (Versatile Impulse Structure Approximation) for macromodeling of system responses with (discrete) time-...
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...
Abstract-- We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based on optimized computation and contention-free routing. Th...
A tunable power amplifier (PA) from 2.1 GHz to 6.0 GHz is presented for multi-standard radios. The proposed multi-band PA can tune the output impedance to 50 over a wide frequency...
Daisuke Imanishi, Jee Young Hong, Kenichi Okada, A...
To cope with an increasing complexity when analyzing analog mismatch in sub-90nm designs, this paper presents a fast non-MonteCarlo method to calculate mismatch in time domain. Th...