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ASPDAC
2010
ACM
171views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Gate delay estimation in STA under dynamic power supply noise
Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki,...
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
ASPDAC
2010
ACM
155views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Efficient model reduction of interconnects via double gramians approximation
The gramian approximation methods have been proposed recently to overcome the high computing costs of classical balanced truncation based reduction methods. But those methods typi...
Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yic...
ASPDAC
2010
ACM
128views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Adaptive power management for real-time event streams
Kai Huang, Luca Santinelli, Jian-Jia Chen, Lothar ...
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
13 years 9 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan