CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
HIPEAC
2007
Springer
14 years 6 months ago
2007
Springer
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
HIPC
2007
Springer
14 years 6 months ago
2007
Springer
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed...
FPL
2007
Springer
14 years 6 months ago
2007
Springer
The effect of kernel operations on cache optimisations in a soft-core reconfigurable system is important for dynamic cache switching design. Considering kernel operations changes ...
NOCS
2007
IEEE
14 years 6 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
NAS
2007
IEEE
14 years 6 months ago
2007
IEEE
: SAN-level caching can manage caching within a global view so that global hot data can be identified and cached. However, two problems may be encountered in the existing SAN-level...
MSS
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
MICRO
2007
IEEE
14 years 6 months ago
2007
IEEE
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...