Sciweavers

HPCA
2008
IEEE
14 years 7 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
HPCA
2008
IEEE
14 years 7 months ago
Branch-mispredict level parallelism (BLP) for control independence
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...
Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin...
HPCA
2008
IEEE
14 years 7 months ago
CMP network-on-chip overlaid with multi-band RF-interconnect
In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on...
M. Frank Chang, Jason Cong, Adam Kaplan, Mishali N...
HPCA
2008
IEEE
14 years 7 months ago
Roughness of microarchitectural design topologies and its implications for optimization
Recent advances in statistical inference and machine learning close the divide between simulation and classical optimization, thereby enabling more rigorous and robust microarchit...
Benjamin C. Lee, David M. Brooks
HPCA
2008
IEEE
14 years 7 months ago
Fabric convergence implications on systems architecture
Converged fabrics that support data, storage, and cluster networking in a unified fashion are desirable for their cost and manageability advantages. Recent trends towards higher-b...
Kevin Leigh, Parthasarathy Ranganathan, Jaspal Sub...
HPCA
2008
IEEE
14 years 7 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
HPCA
2008
IEEE
14 years 7 months ago
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again
Serializing instructions (SIs), such as writes to control registers, have many complex dependencies, and are difficult to execute out-of-order (OoO). To avoid unnecessary complexi...
Philip M. Wells, Gurindar S. Sohi
HPCA
2008
IEEE
14 years 7 months ago
Amdahl's Law in the multicore era
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...
Mark D. Hill
HPCA
2008
IEEE
14 years 7 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
HPCA
2008
IEEE
14 years 7 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...