HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
This paper describes the first infrastructure for integrated studies of the performance and thermal behavior of storage systems. Using microbenchmarks running on this infrastructu...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
Memory bugs are a broad class of bugs that is becoming increasingly common with increasing software complexity, and many of these bugs are also security vulnerabilities. Unfortuna...