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VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
15 years 1 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
VLSID
2007
IEEE
103views VLSI» more  VLSID 2007»
15 years 1 months ago
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Abstract-- This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variation...
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopala...
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
15 years 1 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...
VLSID
2007
IEEE
99views VLSI» more  VLSID 2007»
15 years 1 months ago
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
VLSID
2007
IEEE
100views VLSI» more  VLSID 2007»
15 years 1 months ago
Hardware Efficient Piecewise Linear Branch Predictor
Piecewise linear branch predictor has been demonstrated to have superior prediction accuracy; however, its huge hardware overhead prevents the predictor from being practical in the...
Jiajin Tu, Jian Chen, Lizy K. John
VLSID
2007
IEEE
91views VLSI» more  VLSID 2007»
15 years 1 months ago
Creating a Culture of Innovation
Wim Roelandts
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 1 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
VLSID
2007
IEEE
112views VLSI» more  VLSID 2007»
15 years 1 months ago
Synthesizing "Verification Aware" Models: Why and How?
Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazu...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
15 years 1 months ago
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips
Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices for biochemical analysis. A promising category of microfluidic biochips relie...
Tao Xu, Krishnendu Chakrabarty, Fei Su
VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
15 years 1 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty