Sciweavers

VLSID
2006
IEEE
143views VLSI» more  VLSID 2006»
14 years 1 months ago
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar
VLSID
2006
IEEE
95views VLSI» more  VLSID 2006»
14 years 1 months ago
Design of Embedded Systems with Novel Applications
Robert C. Lacovara, Dhadesugoor R. Vaman
VLSID
2006
IEEE
109views VLSI» more  VLSID 2006»
14 years 1 months ago
Carbon Nanotube Electronics
Ali Javey, Hongjie Dai
VLSID
2006
IEEE
87views VLSI» more  VLSID 2006»
14 years 1 months ago
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...
Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 1 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
VLSID
2006
IEEE
94views VLSI» more  VLSID 2006»
14 years 1 months ago
On the Size and Generation of Minimal N-Detection Tests
The main result of this paper, proved as a theorem, is that a lower bound on the number of test vectors that detect each fault at least N times is N
Kalyana R. Kantipudi
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 1 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
VLSID
2006
IEEE
112views VLSI» more  VLSID 2006»
14 years 1 months ago
Handling Constraints in Multi-Objective GA for Embedded System Design
Design space exploration is central to embedded system design. Typically this is a multi-objective search problem, where performance, power, area etc. are the different optimizati...
Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik ...
VLSID
2006
IEEE
71views VLSI» more  VLSID 2006»
14 years 1 months ago
Clockless Pipelining for Coarse Grain Datapaths
In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting st...
Abdelhalim Alsharqawi, Abdel Ejnioui
SBACPAD
2006
IEEE
148views Hardware» more  SBACPAD 2006»
14 years 1 months ago
Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference
We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inferen...
Vasanth Krishna Namasivayam, Animesh Pathak, Vikto...