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    DAC
    2006
    ACM
    120views Computer Architecture» more  DAC 2006»
    Optimal jumper insertion for antenna avoidance under ratio upper-bound
    15 years 12 days ago
    Optimal jumper insertion for antenna avoidance under ratio upper-bound
    Download  www.ece.northwestern.edu
    Antenna effect may damage gate oxides during plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the ...
    Jia Wang, Hai Zhou
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    DAC
    2006
    ACM
    163views Computer Architecture» more  DAC 2006»
    Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
    15 years 12 days ago
    Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
    Download  homepages.cae.wisc.edu
    Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
    Wei-Shen Wang, Vladik Kreinovich, Michael Orshansk...
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    DAC
    2006
    ACM
    130views Computer Architecture» more  DAC 2006»
    Predicate learning and selective theory deduction for a difference logic solver
    15 years 12 days ago
    Predicate learning and selective theory deduction for a difference logic solver
    Download  www.nec-labs.com
    Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
    Chao Wang, Aarti Gupta, Malay K. Ganai
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    DAC
    2006
    ACM
    156views Computer Architecture» more  DAC 2006»
    Design space exploration using time and resource duality with the ant colony optimization
    15 years 12 days ago
    Design space exploration using time and resource duality with the ant colony optimization
    Download  www.cs.washington.edu
    Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
    Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastne...
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    DAC
    2006
    ACM
    116views Computer Architecture» more  DAC 2006»
    Shielding against design flaws with field repairable control logic
    15 years 12 days ago
    Shielding against design flaws with field repairable control logic
    Download  www.eecs.umich.edu
    Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
    Ilya Wagner, Valeria Bertacco, Todd M. Austin
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    DAC
    2006
    ACM
    82views Computer Architecture» more  DAC 2006»
    Towards the automatic exploration of arithmetic-circuit architectures
    15 years 12 days ago
    Towards the automatic exploration of arithmetic-circuit architectures
    Download  lap.epfl.ch
    Ajay K. Verma, Paolo Ienne
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    DAC
    2006
    ACM
    120views Computer Architecture» more  DAC 2006»
    Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
    15 years 12 days ago
    Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
    Download  www.ece.cmu.edu
    Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
    Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
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    DAC
    2006
    ACM
    104views Computer Architecture» more  DAC 2006»
    A real time budgeting method for module-level-pipelined bus based system using bus scenarios
    15 years 12 days ago
    A real time budgeting method for module-level-pipelined bus based system using bus scenarios
    Download  www.cs.ucr.edu
    In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...
    Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Te...
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    DAC
    2006
    ACM
    130views Computer Architecture» more  DAC 2006»
    Gate sizing: finFETs vs 32nm bulk MOSFETs
    15 years 12 days ago
    Gate sizing: finFETs vs 32nm bulk MOSFETs
    Download  www.cs.tufts.edu
    FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
    Brian Swahn, Soha Hassoun
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    DAC
    2006
    ACM
    138views Computer Architecture» more  DAC 2006»
    Efficient detection and exploitation of infeasible paths for software timing analysis
    15 years 12 days ago
    Efficient detection and exploitation of infeasible paths for software timing analysis
    Download  www.comp.nus.edu.sg
    Accurate estimation of the worst-case execution time (WCET) of a program is important for real-time embedded software. Static WCET estimation involves program path analysis and ar...
    Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, T...
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