DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit thes...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Dynamic Power Management is a design methodology aiming at reducing power consumption of electronic systems, by performing selective shutdown of the idle system resources. The eff...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behavior in a fir...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
We present a novel algorithm based on dynamic programming with binning to find, subject to a given deadline, the minimum-cost coarse-grain hardware/software partitioning and mappin...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The p...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally...