Sciweavers

DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 5 months ago
Framework for Fault Analysis and Test Generation in DRAMs
Abstract: With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory t...
Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. v...
DATE
2005
IEEE
172views Hardware» more  DATE 2005»
14 years 5 months ago
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development
Embedded software design for real time reactive system
Massimo Baleani, Alberto Ferrari, Leonardo Mangeru...
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
14 years 5 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
DATE
2005
IEEE
102views Hardware» more  DATE 2005»
14 years 5 months ago
Statistical Timing Based Optimization using Gate Sizing
Aseem Agarwal, Kaviraj Chopra, David Blaauw
DATE
2005
IEEE
124views Hardware» more  DATE 2005»
14 years 5 months ago
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
Raoul F. Badaoui, Ranga Vemuri
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
14 years 5 months ago
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access
Scratch-pad memory is becoming an important fixture in embedded multimedia systems. It is significantly more efficient than the cache, in performance and power, and has the add...
Mohammed Javed Absar, Francky Catthoor
DATE
2005
IEEE
144views Hardware» more  DATE 2005»
14 years 5 months ago
An Accurate SER Estimation Method Based on Propagation Probability
In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Exper...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 5 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski
DATE
2005
IEEE
149views Hardware» more  DATE 2005»
14 years 5 months ago
A Public-Key Watermarking Technique for IP Designs
— Sharing IP blocks in today’s competitive market poses significant high security risks. Creators and owners of IP designs want assurances that their content will not be illeg...
Amr T. Abdel-Hamid, Sofiène Tahar, El Mosta...