Sciweavers

DATE
2005
IEEE
127views Hardware» more  DATE 2005»
14 years 5 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
14 years 5 months ago
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a ...
G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, F...
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
14 years 5 months ago
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use clus...
Lei Li, Krishnendu Chakrabarty
DATE
2005
IEEE
120views Hardware» more  DATE 2005»
14 years 5 months ago
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Supply voltage scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting...
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 5 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
DATE
2005
IEEE
87views Hardware» more  DATE 2005»
14 years 5 months ago
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
We discuss the problem of Concurrent Error Detection (CED) in a popular class of asynchronous controllers, namely Burst-Mode machines. We first outline the particularities of the...
Sobeeh Almukhaizim, Yiorgos Makris
DATE
2005
IEEE
101views Hardware» more  DATE 2005»
14 years 5 months ago
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
Christophe Alexandre, Hugo Clément, Jean-Pa...
DATE
2005
IEEE
151views Hardware» more  DATE 2005»
14 years 5 months ago
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...
Domenico Barretta, William Fornaciari, Mariagiovan...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 5 months ago
Systematic Figure of Merit Computation for the Design of Pipeline ADC
Ludovic Barrandon, S. Crand, Dominique Houzet