Sciweavers

DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 5 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
DATE
2006
IEEE
72views Hardware» more  DATE 2006»
14 years 5 months ago
HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope
A new methodology is presented to assure numerically reliable integration of the magnetisation slope in the JilesAtherton model of ferromagnetic core hysteresis. Two HDL implement...
Hessa Al-Junaid, Tom J. Kazmierski
DATE
2006
IEEE
75views Hardware» more  DATE 2006»
14 years 5 months ago
Space of DRAM fault models and corresponding testing
Abstract: DRAMs play an important role in the semiconductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of faul...
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
14 years 5 months ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
14 years 5 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
DATE
2006
IEEE
70views Hardware» more  DATE 2006»
14 years 5 months ago
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonj...
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
14 years 5 months ago
Faster exploration of high level design alternatives using UML for better partitions
Partitioning is a time consuming and computationally complex optimization problem in the codesign of hardware software systems. The stringent time-to-market requirements have resu...
Waseem Ahmed, Doug Myers
DATE
2006
IEEE
126views Hardware» more  DATE 2006»
14 years 5 months ago
Analysis and modeling of power grid transmission lines
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
J. Balachandran, Steven Brebels, G. Carchon, T. We...