DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Multi-core architectures introduce a new granularity at which process variations may occur, yielding asymmetry among cores that were designed—and that software expects—to be s...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper proposes a novel algorithm that, given a data-flow graph and an input/output constraint, enumerates all convex subgraphs under the given constraint in polynomial time ...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Economic testing of small devices like LCD drivers is a real challenge. In this paper we describe an approach where a production tester is extended by a memory test engine (MTE). ...