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DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 5 months ago
Accurate and scalable reliability analysis of logic circuits
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
Mihir R. Choudhury, Kartik Mohanram
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 5 months ago
A new hybrid solution to boost SAT solver performance
Due to the widespread demands for efficient SAT solvers in Electronic Design Automation applications, methods to boost the performance of the SAT solver are highly desired. We pr...
Lei Fang, Michael S. Hsiao
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
14 years 5 months ago
Test quality analysis and improvement for an embedded asynchronous FIFO
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clock...
Tobias Dubois, Erik Jan Marinissen, Mohamed Aziman...
DATE
2007
IEEE
111views Hardware» more  DATE 2007»
14 years 5 months ago
Cost-aware capacity optimization in dynamic multi-hop WSNs
Low energy consumption and load balancing are required for enhancing lifetime at Wireless Sensor Networks (WSN). In addition, network dynamics and different delay, throughput, and...
Jukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, M...
DATE
2007
IEEE
55views Hardware» more  DATE 2007»
14 years 5 months ago
Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry
RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due t...
Tejasvi Das, P. R. Mukund
DATE
2007
IEEE
125views Hardware» more  DATE 2007»
14 years 5 months ago
Simulation platform for UHF RFID
1 Developing modern integrated and embedded systems require well-designed processes to ensure flexibility and independency. These features are related to exchangeability of hardw...
Vojtech Derbek, Christian Steger, Reinhold Weiss, ...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 5 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 5 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
DATE
2007
IEEE
167views Hardware» more  DATE 2007»
14 years 5 months ago
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multip
We present a decomposition strategy to speed up constraint optimization for a representative multiprocessor scheduling problem. In the manner of Benders decomposition, our techniq...
Nadathur Satish, Kaushik Ravindran, Kurt Keutzer
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
14 years 5 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...