DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
In this paper, a two-step methodology is introduced to analyse the mapping of Cyclostationary Feature Detection (CFD) onto a multi-core processing platform. In the first step, th...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Abstract: An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical,...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a n...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper describes a novel test method for continuous-time adaptive equalizers. This technique applies a two-sinusoidal-tone signal as stimulus and includes an RMS detector for ...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...