Sciweavers

DATE
2007
IEEE
172views Hardware» more  DATE 2007»
14 years 5 months ago
Diagnosis, modeling and tolerance of scan chain hold-time violations
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
Ozgur Sinanoglu, Philip Schremmer
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 5 months ago
A multi-core debug platform for NoC-based systems
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
Shan Tang, Qiang Xu
DATE
2007
IEEE
108views Hardware» more  DATE 2007»
14 years 5 months ago
Evaluation of design for reliability techniques in embedded flash memories
Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor conce...
Benoît Godard, Jean Michel Daga, Lionel Torr...
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
14 years 5 months ago
Slow write driver faults in 65nm SRAM technology: analysis and March test solution
∗ This paper presents an analysis of the electrical origins of Slow Write Driver Faults (SWDFs) [1] that may affect SRAM write drivers in 65nm technology. This type of fault is t...
Alexandre Ney, Patrick Girard, Christian Landrault...
DATE
2007
IEEE
98views Hardware» more  DATE 2007»
14 years 5 months ago
A one-shot configurable-cache tuner for improved energy and performance
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A...
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 5 months ago
Architectural leakage-aware management of partitioned scratchpad memories
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be ev...
Olga Golubeva, Mirko Loghi, Massimo Poncino, Enric...
DATE
2007
IEEE
103views Hardware» more  DATE 2007»
14 years 5 months ago
Flexible hardware reduction for elliptic curve cryptography in GF(2m)
In this paper we discuss two ways to provide flexible hardware support for the reduction step in Elliptic Curve Cryptography in binary fields (GF(2m )). In our first approach w...
Steffen Peter, Peter Langendörfer, Krzysztof ...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 5 months ago
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
We propose a robust circuit-based Boolean Satisfiability (SAT) solver, QuteSAT, that can be applied to complex circuit netlist structure. Several novel techniques are proposed in ...
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 5 months ago
Automatic synthesis of compressor trees: reevaluating large counters
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
Ajay K. Verma, Paolo Ienne