DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Lasers can be used by hackers to situations to inject faults in circuits and induce security flaws. On-line detection mechanisms are classically proposed to counter such attacks, ...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the ...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...