Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher p...
Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V...
This paper presents the Pareto Calculator, a tool for compositional computation of Pareto points, based on the algebra of Pareto points. The tool is a useful instrument for multidi...
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosi...
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values ...
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Ta...