DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...