Sciweavers

DATE
2008
IEEE
142views Hardware» more  DATE 2008»
14 years 7 months ago
Developing Mesochronous Synchronizers to Enable 3D NoCs
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
Igor Loi, Federico Angiolini, Luca Benini
DATE
2008
IEEE
71views Hardware» more  DATE 2008»
14 years 7 months ago
Efficient Symbolic Simulation of Low Level Software
Tamarah Arons, Elad Elster, Shlomit Ozer, Jonathan...
DATE
2008
IEEE
95views Hardware» more  DATE 2008»
14 years 7 months ago
Improvements in Polynomial-Time Feasibility Testing for EDF
This paper presents two fully polynomial-time sufficient feasibility tests for EDF when considering periodic tasks with arbitrary deadlines and preemptive scheduling on uniproces...
Alejandro Masrur, Sebastian Drossler, Georg Farber
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
14 years 7 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
14 years 7 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
DATE
2008
IEEE
140views Hardware» more  DATE 2008»
14 years 7 months ago
FPGA Design for Algebraic Tori-Based Public-Key Cryptography
Algebraic torus-based cryptosystems are an alternative for Public-Key Cryptography (PKC). It maintains the security of a larger group while the actual computations are performed i...
Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid ...
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 7 months ago
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Ta...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 7 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...
DATE
2008
IEEE
82views Hardware» more  DATE 2008»
14 years 7 months ago
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications
This paper presents the implementation and experimental characterization of a reconfigurable ΣΔ modulator intended for multi-mode wireless receivers that is capable to perform t...
Alonso Morgado, Rocio del Río, José ...
DATE
2008
IEEE
137views Hardware» more  DATE 2008»
14 years 7 months ago
SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
In this paper we describe a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parametric s...
Jorge Fernandez Villena, Luis Miguel Silveira