Sciweavers

DATE
2008
IEEE
82views Hardware» more  DATE 2008»
14 years 7 months ago
Periodic Steady-State Analysis Augmented with Design Equality Constraints
— A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performan...
Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kar...
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
14 years 7 months ago
EPIC: Ending Piracy of Integrated Circuits
As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized exces...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 7 months ago
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor
A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent function...
Trevor Meyerowitz, Alberto L. Sangiovanni-Vincente...
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
14 years 7 months ago
Software Protection Mechanisms for Dependable Systems
We expect that in future commodity hardware will be used in safety critical applications. But the used commodity microprocessors will become less reliable because of decreasing fe...
Ute Wappler, Martin Muller
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
14 years 7 months ago
Novel Pin Assignment Algorithms for Components with Very High Pin Counts
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of s...
Tilo Meister, Jens Lienig, Gisbert Thomke
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 7 months ago
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
Anshuman Chandra, Felix Ng, Rohit Kapur
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 7 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja
DATE
2008
IEEE
139views Hardware» more  DATE 2008»
14 years 7 months ago
Scan Chain Organization for Embedded Diagnosis
Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel...
Melanie Elm, Hans-Joachim Wunderlich
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 7 months ago
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches
We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits...
Almitra Pradhan, Ranga Vemuri