Sciweavers

DATE
2008
IEEE
226views Hardware» more  DATE 2008»
14 years 7 months ago
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation
Abstract— We present a general method to evaluate RF BuiltIn Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construc...
Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, ...
DATE
2008
IEEE
78views Hardware» more  DATE 2008»
14 years 7 months ago
Transistor-Specific Delay Modeling for SSTA
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
Brian Cline, Kaviraj Chopra, David Blaauw, Andres ...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 7 months ago
Modeling Event Stream Hierarchies with Hierarchical Event Models
Compositional Scheduling Analysis couples local scheduling analysis via event streams. While local analysis has successfully been extended to include hierarchical scheduling strat...
Jonas Rox, Rolf Ernst
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 7 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 7 months ago
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems
Failure Mode and Effects Analysis (FMEA) is a wellknown technique widely used for safety assessment in the area of safety-critical systems. However, FMEA is traditionally done man...
Jonas Elmqvist, Simin Nadjm-Tehrani
DATE
2008
IEEE
100views Hardware» more  DATE 2008»
14 years 7 months ago
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs
When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able t...
Bastian Ristau, Torsten Limberg, Gerhard Fettweis
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
14 years 7 months ago
Symbolic Reliability Analysis and Optimization of ECU Networks
Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases ...
Michael Glaß, Martin Lukasiewycz, Felix Reim...
DATE
2008
IEEE
129views Hardware» more  DATE 2008»
14 years 7 months ago
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...
Dinesh Pamunuwa
DATE
2008
IEEE
123views Hardware» more  DATE 2008»
14 years 7 months ago
Test Strategies for Low Power Devices
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing...
C. P. Ravikumar, M. Hirech, X. Wen