Abstract— We present a general method to evaluate RF BuiltIn Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construc...
Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, ...
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
Brian Cline, Kaviraj Chopra, David Blaauw, Andres ...
Compositional Scheduling Analysis couples local scheduling analysis via event streams. While local analysis has successfully been extended to include hierarchical scheduling strat...
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Failure Mode and Effects Analysis (FMEA) is a wellknown technique widely used for safety assessment in the area of safety-critical systems. However, FMEA is traditionally done man...
When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able t...
Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases ...
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing...