Sciweavers

DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 7 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
14 years 7 months ago
Semantics for Model-Based Validation of Continuous/Discrete Systems
Continuous and discrete components can be integrated in diverse systems including defense, medical, electronic, communication, and automotive applications. Given the heterogeneity...
Luiza Gheorghe, Faouzi Bouchhima, Gabriela Nicoles...
DATE
2008
IEEE
130views Hardware» more  DATE 2008»
14 years 7 months ago
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs
—Increasing integrated circuit (IC) power densities and temperatures may hamper multiprocessor system-on-chip (MPSoC) use in hard real-time systems. This article formalizes the t...
Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 7 months ago
Parametric Throughput Analysis of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) have proved to be a very successful tool for modeling, analysis and synthesis of multimedia applications targeted at both single- and multiproc...
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, ...
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
14 years 7 months ago
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation
Comparator-based switched capacitor (CBSC) circuits present an alternative approach to designing sampled data systems based on the principle of detecting a virtual ground conditio...
Massoud Momeni, Petru Bogdan Bacinschi, Manfred Gl...
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
14 years 7 months ago
Compositional design of isochronous systems
The synchronous modeling paradigm provides strong execution correctness guarantees to embedded system design while making minimal environmental assumptions. In most related framew...
Jean-Pierre Talpin, Julien Ouy, Loïc Besnard,...
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 7 months ago
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimso...