With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Denn...
Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance...
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applicat...
Francesco Poletti, Paul Marchal, David Atienza, Lu...
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
In this paper, we systematically define three transaction level TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP...
The desynchronization approach combines a traditional synchronous specification style with a robust asynchronous implementation model. The main contribution of this paper is the d...
Abhijit Davare, Kelvin Lwin, Alex Kondratyev, Albe...
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...