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    IAJIT
    2010
    84views more  IAJIT 2010»
    A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
    13 years 10 months ago
    A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
    Download  www.ccis2k.org
    : A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...
    Bashar Al-Khalifa
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    JMM2
    2007
    118views more  JMM2 2007»
    FPGA-based Real-time Optical Flow Algorithm Design and Implementation
    13 years 11 months ago
    FPGA-based Real-time Optical Flow Algorithm Design and Implementation
    Download  www.academypublisher.com
    —Optical flow algorithms are difficult to apply to robotic vision applications in practice because of their extremely high computational and frame rate requirements. In most case...
    Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson
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    TCAD
    2008
    112views more  TCAD 2008»
    Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
    13 years 11 months ago
    Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
    Download  www.ece.ualberta.ca
    Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
    Yu Hu, Victor Shih, Rupak Majumdar, Lei He
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    ISCA
    2006
    IEEE
    114views Hardware» more  ISCA 2006»
    Using System-on-a-Programmable-Chip Technology to Design Embedded Systems
    13 years 11 months ago
    Using System-on-a-Programmable-Chip Technology to Design Embedded Systems
    Download  users.ece.gatech.edu
    This paper describes the tools, techniques, and devices used to design embedded products with system
    James O. Hamblen, Tyson S. Hall
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    CVIU
    2010
    115views more  CVIU 2010»
    A modified model for the Lobula Giant Movement Detector and its FPGA implementation
    13 years 11 months ago
    A modified model for the Lobula Giant Movement Detector and its FPGA implementation
    Download  eprints.lincoln.ac.uk
    Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
    Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
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    ESANN
    2006
    134views Neural Networks» more  ESANN 2006»
    Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
    14 years 25 days ago
    Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
    Download  www.dice.ucl.ac.be
    Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
    Benjamin Schrauwen, Jan M. Van Campenhout
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    CSREAESA
    2006
    86views Embedded Systems» more  CSREAESA 2006»
    In-House Built Bipedal Walking Robot
    14 years 25 days ago
    In-House Built Bipedal Walking Robot
    Download  ww1.ucmss.com
    In this project, an in-house built bipedal walking Robot uses two direct current gear motors to power its legs. Each leg could bend at the knee to assist the walking routines. In ...
    Kok-Swee Sim, Yee Kin Lum, Chih Ping Tso
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    FPL
    2008
    Springer
    117views Hardware» more  FPL 2008»
    A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
    14 years 1 months ago
    A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
    Download  ccc.inaoep.mx
    This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
    Roberto Perez-Andrade, René Cumplido, Claud...
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    ISCAS
    1995
    IEEE
    91views Hardware» more  ISCAS 1995»
    An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
    14 years 3 months ago
    An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
    Download  www.cecs.uci.edu
    Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
    W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
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    FPL
    2000
    Springer
    95views Hardware» more  FPL 2000»
    It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures
    14 years 3 months ago
    It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures
    Download  www.algotronix.com
    Following the simple Programmable Logic Device (SPLD) and Field Programmable Gate Array (FPGA) generations a third generation of programmable logic technologies is now reaching the...
    Tom Kean
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