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FPL
2003
Springer
59views Hardware» more  FPL 2003»
14 years 4 months ago
Networks on Chip as Hardware Components of an OS for Reconfigurable Systems
Théodore Marescaux, Jean-Yves Mignolet, And...
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 4 months ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...
FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 4 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
FPL
2003
Springer
75views Hardware» more  FPL 2003»
14 years 4 months ago
Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware
Shaomeng Li, Jim Torresen, Oddvar Sørå...
FPL
2003
Springer
113views Hardware» more  FPL 2003»
14 years 4 months ago
Non-uniform Segmentation for Hardware Function Evaluation
This paper presents a method for evaluating functions in hardware based on polynomial approximation with non-uniform segments. The novel use of nonuniform segments enables us to ap...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
FPL
2003
Springer
146views Hardware» more  FPL 2003»
14 years 4 months ago
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
Sami Khawam, Tughrul Arslan, Fred Westall
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 4 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
FPL
2003
Springer
136views Hardware» more  FPL 2003»
14 years 4 months ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller
FPL
2003
Springer
74views Hardware» more  FPL 2003»
14 years 4 months ago
Reconfigurable Circuits Using Hybrid Hall Effect Devices
Abstract. Hybrid Hall effect (HHE) devices are a new class of reconfigurable logic devices that incorporate ferromagnetic elements to deliver nonvolatile operation. A single HHE de...
Steve Ferrera, Nicholas P. Carter
FPL
2003
Springer
128views Hardware» more  FPL 2003»
14 years 4 months ago
A Generic Architecture for Integrated Smart Transducers
Abstract. A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system...
Martin Delvai, Ulrike Eisenmann, Wilfried Elmenrei...