DATE
2010
IEEE
14 years 20 days ago
2010
IEEE
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
ISCA
2003
IEEE
14 years 26 days ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
FCCM
2003
IEEE
14 years 26 days ago
2003
IEEE
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
SAMOS
2004
Springer
14 years 28 days ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
RTCSA
2006
IEEE
14 years 1 months ago
2006
IEEE
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper describes a new basis for the implementation of a shifter functional unit. We present a design based on the inverse butterfly and butterfly datapath circuits that perfo...