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ATS
2009
IEEE
185views Hardware» more  ATS 2009»
14 years 4 months ago
Customized Algorithms for High Performance Memory Test in Advanced Technology Node
Embedded memory quality is critical to overall chip quality. New defect mechanisms that occur at advanced process nodes (65nm and below) are often more pronounced in memories due ...
Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu
ATS
2009
IEEE
126views Hardware» more  ATS 2009»
14 years 4 months ago
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
—In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper w...
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai,...
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
14 years 4 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...
ATS
2009
IEEE
119views Hardware» more  ATS 2009»
14 years 4 months ago
Fault Diagnosis Using Test Primitives in Random Access Memories
As diagnostic testing for memory devices increasingly gains in importance, companies are looking for flexible, cost effective methods to perform diagnostics on their failing devi...
Zaid Al-Ars, Said Hamdioui
ATS
2009
IEEE
117views Hardware» more  ATS 2009»
14 years 4 months ago
N-distinguishing Tests for Enhanced Defect Diagnosis
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets,...
Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith...
ATS
2009
IEEE
99views Hardware» more  ATS 2009»
14 years 4 months ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab
ATS
2009
IEEE
138views Hardware» more  ATS 2009»
14 years 4 months ago
Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks
Power distribution network (PDN) designs for today’s high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and henc...
Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
14 years 4 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
ATS
2009
IEEE
113views Hardware» more  ATS 2009»
14 years 4 months ago
Deterministic Algorithms for ATPG under Leakage Constraints
—Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the re...
Gorschwin Fey