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3DIC
2009
IEEE
258views Hardware» more  3DIC 2009»
14 years 4 months ago
A capacitive coupling interface with high sensitivity for wireless wafer testing
—A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver c...
Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 4 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
3DIC
2009
IEEE
138views Hardware» more  3DIC 2009»
14 years 4 months ago
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
Chang-Lee Chen, D.-R. Yost, Jeffrey M. Knecht, Dav...
3DIC
2009
IEEE
184views Hardware» more  3DIC 2009»
14 years 4 months ago
Architectural evaluation of 3D stacked RRAM caches
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
Dean L. Lewis, HsienHsin S. Lee
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
14 years 4 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
3DIC
2009
IEEE
120views Hardware» more  3DIC 2009»
14 years 4 months ago
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-a...
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuw...
FPGA
2010
ACM
178views FPGA» more  FPGA 2010»
14 years 4 months ago
Designing hardware with dynamic memory abstraction
Jirí Simsa, Satnam Singh
FPGA
2010
ACM
201views FPGA» more  FPGA 2010»
14 years 4 months ago
Scalable network virtualization using FPGAs
Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong L...
FLOPS
2010
Springer
14 years 4 months ago
Haskell Type Constraints Unleashed
Dominic A. Orchard, Tom Schrijvers
FLOPS
2010
Springer
14 years 4 months ago
Code Generation via Higher-Order Rewrite Systems
Abstract. We present the meta-theory behind the code generation facilities of Isabelle/HOL. To bridge the gap between the source (higherorder logic with type classes) and the many ...
Florian Haftmann, Tobias Nipkow