ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
Redundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire wa. Addition of wa makes wt redundant and hence removab...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
