ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
Interconnect structures including dielectrics can be modeled by an integral equation method using volume currents and surface charges for the conductors, and volume polarization c...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. Certain devic...
ICCAD
2001
IEEE
14 years 10 months ago
2001
IEEE
This paper presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high per...