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FPL
2008
Springer
103views Hardware» more  FPL 2008»
13 years 10 months ago
No-break dynamic defragmentation of reconfigurable devices
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules ...
Sándor P. Fekete, Tom Kamphans, Nils Schwee...
FPL
2008
Springer
131views Hardware» more  FPL 2008»
13 years 10 months ago
Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis
Cryptanalysis of symmetric and asymmetric ciphers is a challenging task due to the enormous amount of involved computations. To tackle this computational complexity, usually the e...
Tim Güneysu, Christof Paar, Gerd Pfeiffer, Ma...
FPL
2008
Springer
100views Hardware» more  FPL 2008»
13 years 10 months ago
A portable abstraction layer for hardware threads
Enno Lübbers, Marco Platzner
FPL
2008
Springer
143views Hardware» more  FPL 2008»
13 years 10 months ago
Fast toggle rate computation for FPGA circuits
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
Tomasz S. Czajkowski, Stephen Dean Brown
FPL
2008
Springer
91views Hardware» more  FPL 2008»
13 years 10 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 10 months ago
Shared reconfigurable architectures for CMPS
This paper investigates reconfigurable architectures suitable for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfi...
Matthew A. Watkins, Mark J. Cianchetti, David H. A...
FPL
2008
Springer
175views Hardware» more  FPL 2008»
13 years 10 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
ICES
2007
Springer
88views Hardware» more  ICES 2007»
13 years 10 months ago
Evolving and Analysing "Useful" Redundant Logic
Abstract. Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to ...
Asbjørn Djupdal, Pauline C. Haddow
ICES
2007
Springer
70views Hardware» more  ICES 2007»
13 years 10 months ago
Evolutionary Design of Generic Combinational Multipliers Using Development
Combinational multipliers represent a class of circuits that is usually considered to be hard to design by means of the evolutionary techniques. However, experiments conducted unde...
Michal Bidlo
ICCAD
2007
IEEE
119views Hardware» more  ICCAD 2007»
13 years 10 months ago
IntSim: A CAD tool for optimization of multilevel interconnect networks
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffre...