Sciweavers

FPL
2008
Springer
153views Hardware» more  FPL 2008»
13 years 10 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
FPL
2008
Springer
110views Hardware» more  FPL 2008»
13 years 10 months ago
Automatic generation of run-time parameterizable configurations
In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (Field Programmable Gate Arrays) can ...
Karel Bruneel, Dirk Stroobandt
FPL
2008
Springer
98views Hardware» more  FPL 2008»
13 years 10 months ago
Comparing throughput and power consumption in both sequential and reconfigurable processors
Recent improvements in the memory capacity of Field Programmable Gate Arrays (FPGAs) have spurred interest in using the devices for arithmetic floating-point operations. However, ...
Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady
FPL
2008
Springer
117views Hardware» more  FPL 2008»
13 years 10 months ago
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
Roberto Perez-Andrade, René Cumplido, Claud...
FPL
2008
Springer
126views Hardware» more  FPL 2008»
13 years 10 months ago
Customized Reconfigurable Interconnection Networks for multiple application SOCS
A Customized Reconfigurable Interconnection Network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirem...
Hongbing Fan, Jason Ernst, Yu-Liang Wu
FPL
2008
Springer
163views Hardware» more  FPL 2008»
13 years 10 months ago
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenc...
FPL
2008
Springer
254views Hardware» more  FPL 2008»
13 years 10 months ago
Digital hilbert transformers for FPGA-based phase-locked loops
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
Martin Kumm, M. Shahab Sanjari
FPL
2008
Springer
157views Hardware» more  FPL 2008»
13 years 10 months ago
Chosen-message SPA attacks against FPGA-based RSA hardware implementations
This paper presents SPA (Simple Power Analysis) attacks against public-key cryptosystems implemented on an FPGA platform. The SPA attack investigates a power waveform generated by...
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Ak...
FPL
2008
Springer
99views Hardware» more  FPL 2008»
13 years 10 months ago
ATCA-based computation platform for data acquisition and triggering in particle physics experiments
Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, W...
FPL
2008
Springer
117views Hardware» more  FPL 2008»
13 years 10 months ago
On-the-fly attestation of reconfigurable hardware
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfi...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa