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FPL
2008
Springer
124views Hardware» more  FPL 2008»
13 years 10 months ago
Direct sigma-delta modulated signal processing in FPGA
The effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular...
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-S...
ISLPED
2007
ACM
96views Hardware» more  ISLPED 2007»
13 years 10 months ago
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
Debabrata Mohapatra, Georgios Karakonstantis, Kaus...
FPL
2008
Springer
96views Hardware» more  FPL 2008»
13 years 10 months ago
Low-latency high-bandwidth HW/SW communication in a virtual memory environment
Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of de...
Holger Lange, Andreas Koch
FPL
2008
Springer
119views Hardware» more  FPL 2008»
13 years 10 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...
FPL
2008
Springer
120views Hardware» more  FPL 2008»
13 years 10 months ago
An FPGA-based implementation of the MINRES algorithm
Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. The solution of a system of linea...
David Boland, George A. Constantinides
FPL
2008
Springer
107views Hardware» more  FPL 2008»
13 years 10 months ago
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 10 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
FPL
2008
Springer
137views Hardware» more  FPL 2008»
13 years 10 months ago
FPGA acceleration of Monte-Carlo based credit derivative pricing
In recent years the financial world has seen an increasing demand for faster risk simulations, driven by growth in client portfolios. Traditionally many financial models employ Mo...
Alexander Kaganov, Paul Chow, Asif Lakhany
FPL
2008
Springer
111views Hardware» more  FPL 2008»
13 years 10 months ago
Hyperreconfigurable architectures
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increa...
Sebastian Lange, Martin Middendorf
FPL
2008
Springer
122views Hardware» more  FPL 2008»
13 years 10 months ago
Mining Association Rules with systolic trees
Association Rules Mining (ARM) algorithms are designed to find sets of frequently occurring items in large databases. ARM applications have found their way into a variety of field...
Song Sun, Joseph Zambreno