Sciweavers

ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
14 years 6 days ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
ASPDAC
1995
ACM
95views Hardware» more  ASPDAC 1995»
14 years 6 days ago
A hardware-oriented design for weighted median filters
Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao
ASPDAC
1995
ACM
58views Hardware» more  ASPDAC 1995»
14 years 6 days ago
A tool for measuring quality of test pattern for LSIs' functional design
Takashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Ken...
ASAP
1995
IEEE
84views Hardware» more  ASAP 1995»
14 years 6 days ago
Implementation of Parallel Arithmetic in a Cellular Automaton
Richard K. Squier, Kenneth Steiglitz, Mariusz H. J...
ASAP
1995
IEEE
145views Hardware» more  ASAP 1995»
14 years 6 days ago
An array processor for inner product computations using a Fermat number ALU
This paper explores an architecture for parallel independent computations of inner products over the direct product ring . The structure is based on the polynomial mapping of the ...
Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, Wil...
DATE
1997
IEEE
109views Hardware» more  DATE 1997»
14 years 6 days ago
Sequential circuit test generation using dynamic state traversal
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
CHARME
1997
Springer
105views Hardware» more  CHARME 1997»
14 years 6 days ago
Simulation-based verification of network protocols performance
Formal verification techniques need to deal with the complexity of the systems rified. Most often, this problem is solved by taking an abstract model of the system and aiming at a...
Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Pa...
CAV
1997
Springer
102views Hardware» more  CAV 1997»
14 years 6 days ago
Efficient Model Checking Using Tabled Resolution
We demonstrate the feasibility of using the XSB tabled logic programming system as a programmable fixed-point engine for implementing efficient local model checkers. In particular,...
Y. S. Ramakrishna, C. R. Ramakrishnan, I. V. Ramak...
PACS
2000
Springer
118views Hardware» more  PACS 2000»
14 years 6 days ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....