ASYNC
1997
IEEE
14 years 6 days ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
ASYNC
1997
IEEE
14 years 6 days ago
1997
IEEE
Wediscuss response timeproperties of linear arrays and tree-like arrays of cells with various handshake communication behaviours. The response times of a networkare the delays bet...
ASYNC
1997
IEEE
14 years 6 days ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
ASAP
1997
IEEE
14 years 6 days ago
1997
IEEE
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
ASAP
1997
IEEE
14 years 6 days ago
1997
IEEE
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to ...
ASAP
1997
IEEE
14 years 6 days ago
1997
IEEE
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
MICRO
2000
IEEE
14 years 6 days ago
2000
IEEE
Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and...
MICRO
2000
IEEE
14 years 6 days ago
2000
IEEE
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
MICRO
2000
IEEE
14 years 6 days ago
2000
IEEE
While technology is delivering increasingly sophisticated and powerful chip designs, it is also imposing alarmingly high energy requirements on the chips. One way to address this ...
MICRO
2000
IEEE
14 years 6 days ago
2000
IEEE
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...