EH
2000
IEEE
14 years 7 days ago
2000
IEEE
The differences between electronics design through artificial evolution and through conventional methods have the consequence that evolved circuits may take unusual leverage from ...
DATE
2000
IEEE
14 years 7 days ago
2000
IEEE
The classical solving approach for two-level logic minimisation reduces the problem to a special case of unate covering and attacks the latter with a (possibly limited) branch-and...
DATE
2010
IEEE
14 years 7 days ago
2010
IEEE
Abstract. We propose an approach to scenario-based analysis and synthesis of real-time embedded systems. The inter-process behaviors of a system are modeled as a set of driving uni...
CAV
2000
Springer
14 years 8 days ago
2000
Springer
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
CAV
2000
Springer
14 years 8 days ago
2000
Springer
xample-Guided Abstraction Refinement for Symbolic Model Checking EDMUND CLARKE YUAN LU Carnegie Mellon University, Pittsburgh, Pennsylvania Broadcom Co., San Jose, California ORNA ...
CAV
2000
Springer
14 years 8 days ago
2000
Springer
CAV
2000
Springer
14 years 8 days ago
2000
Springer
Hierarchical state machines is a popular visual formalism for software specifications. To apply automated analysis to such specifications, the traditional approach is to compile th...
CARDIS
2000
Springer
14 years 8 days ago
2000
Springer
This paper reports on an effort to increase the reliability of JavaCard-based smart cards by means of formal specification and verification of JavaCard source code. As a first ste...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
We have developed a new GA hardware called GAA-I (Genetic Algorithm Accelerator-I), in which the crossover operator to be applied to each individual was dynamically selected during...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
