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IMS
2000
125views Hardware» more  IMS 2000»
14 years 7 days ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
IMS
2000
145views Hardware» more  IMS 2000»
14 years 7 days ago
FlexCache: A Framework for Flexible Compiler Generated Data Caching
Csaba Andras Moritz, Matthew Frank, Saman P. Amara...
IMS
2000
123views Hardware» more  IMS 2000»
14 years 7 days ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...
IMS
2000
115views Hardware» more  IMS 2000»
14 years 7 days ago
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Jose...
ITC
1998
IEEE
126views Hardware» more  ITC 1998»
14 years 7 days ago
A comprehensive approach to the partial scan problem using implicit state enumeration
This paper presents a novel technique to evaluate the noncontrollability measures of state registers for partial scan design. Our model uses implicit techniques for finite state ma...
Priyank Kalla, Maciej J. Ciesielski
ITC
1998
IEEE
66views Hardware» more  ITC 1998»
14 years 7 days ago
A novel combinational testability analysis by considering signal correlation
Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chi...
ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
14 years 7 days ago
New efficient algorithms for computing effective capacitance
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
Andrew B. Kahng, Sudhakar Muddu
ISLPED
1998
ACM
72views Hardware» more  ISLPED 1998»
14 years 7 days ago
Power invariant vector compaction based on bit clustering and temporal partitioning
Nicola Dragone, Roberto Zafalon, Carlo Guardiani, ...
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
14 years 7 days ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
ISCA
1998
IEEE
135views Hardware» more  ISCA 1998»
14 years 7 days ago
Branch Prediction Based on Universal Data Compression Algorithms
Data compression and prediction are closely related. Thus prediction methods based on data compression algorithms have been suggested for the branch prediction problem. In this wo...
Eitan Federovsky, Meir Feder, Shlomo Weiss