ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
- This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow ...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to re...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-reschedul...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
The paper presents an application specific Java processor including reconfigurabilities, which is a DLX like pipeline processor with 5 stages and executes Java byte codes directly....
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a progr...
ASPDAC
2000
ACM
14 years 8 days ago
2000
ACM
ASAP
2000
IEEE
14 years 8 days ago
2000
IEEE
ASAP
2000
IEEE
14 years 8 days ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
CHARME
2003
Springer
14 years 9 days ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...