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DATE
2006
IEEE
97views Hardware» more  DATE 2006»
14 years 10 days ago
Monolithic verification of deep pipelines with collapsed flushing
We introduce collapsed flushing, a new flushing-based refinement map for automatically verifying safety and liveness properties of term-level pipelined machine models. We also pre...
Roma Kane, Panagiotis Manolios, Sudarshan K. Srini...
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
14 years 10 days ago
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
Lakshmi N. Chakrapani, Bilge E. S. Akgul, Suresh C...
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
14 years 10 days ago
Platform-based design of wireless sensor networks for industrial applications
We present a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN). While the method is quite general, we use extensively an exa...
Alvise Bonivento, Luca P. Carloni, Alberto L. Sang...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 10 days ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
14 years 10 days ago
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed t...
Alexandros Bartzas, Stylianos Mamagkakis, Georgios...
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
14 years 10 days ago
Hardware debugging method based on signal transitions and transactions
- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
Nobuyuki Ohba, Kohji Takano
FPL
2004
Springer
143views Hardware» more  FPL 2004»
14 years 11 days ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
FPL
2004
Springer
164views Hardware» more  FPL 2004»
14 years 11 days ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
FPL
2004
Springer
119views Hardware» more  FPL 2004»
14 years 11 days ago
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
Sandeep S. Kumar, Christof Paar