Sciweavers

DSD
2006
IEEE
95views Hardware» more  DSD 2006»
14 years 10 days ago
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
Zhonghai Lu, Ingo Sander, Axel Jantsch
DEPCOS
2006
IEEE
85views Hardware» more  DEPCOS 2006»
14 years 10 days ago
Survey of Recovery Schemes in MPLS Networks
Luísa Jorge, Teresa Gomes
DDECS
2006
IEEE
83views Hardware» more  DDECS 2006»
14 years 10 days ago
Embedded Self Repair by Transistor and Gate Level Reconfiguration
René Kothe, Heinrich Theodor Vierhaus, Tors...
DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
14 years 10 days ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
14 years 10 days ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
14 years 10 days ago
A time-triggered ethernet (TTE) switch
This paper presents the design of a Time-Triggered Ethernet (TTE) Switch, which is one of the core units of the Time-Triggered Ethernet system. Time-triggered Ethernet is a commun...
Klaus Steinhammer, Petr Grillinger, Astrit Ademaj,...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
14 years 10 days ago
Satisfiability-based framework for enabling side-channel attacks on cryptographic software
- Many electronic systems contain implementations of cryptographic algorithms in order to provide security. It is well known that cryptographic algorithms, irrespective of their th...
Nachiketh R. Potlapally, Anand Raghunathan, Srivat...
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
14 years 10 days ago
Compiler-driven FPGA-area allocation for reconfigurable computing
In this paper, we propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem o...
Elena Moscu Panainte, Koen Bertels, Stamatis Vassi...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 10 days ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 10 days ago
Battery-aware code partitioning for a text to speech system
The advent of multi-core embedded processors has brought along new challenges for embedded system design. This paper presents an efficient, battery aware, code partitioning techni...
Anirban Lahiri, Anupam Basu, Monojit Choudhury, Sr...